The present disclosure relates to an electronic equipment system having a large-scale integration (LSI) such as a system LSI (semiconductor integrated circuit), and more particularly to an electronic equipment system in which adjustment against fabrication variations of the LSI, for example, is possible.
Conventionally, in order to improve the performance of LSIs to meet specifications required for electronic equipment systems, techniques of adjusting circuit characteristics of the inside of the LSIs using anti-fuses and fuses have been actively used (see Japanese Patent Publication No. 2002-42472 (Patent Document 1), for example). Specifically, Patent Document 1 describes techniques of adjusting the input capacitance of an input terminal, the phase of an internal clock, and the refresh cycle of a DRAM, as circuit characteristics of the inside of LSIs, using anti-fuses. In such an LSI, when the input capacitance exceeds a specified range in a testing process, for example, an anti-fuse can be programmed to hold information for adjusting the input capacitance. At power-up of the LSI, the circuit path can be changed based on the information held in the anti-fuse, so that the input capacitance can be adjusted. With this adjustment, in actual use of the LSI, the input capacitance is allowed to fall within a predetermined specified range at any time, and thus fabrication variations can be easily addressed. The DRAM refresh cycle and the like can also be adjusted in similar ways: that is, a circuit characteristic of the inside of an LSI can be adjusted by programming an anti-fuse so that the characteristic falls within its specified range in a testing process of the LSI.